Henrik Glader

Henrik Glader
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23 hours ago Commented That was easy = ) I created a new project "GCC for Renesas RX C/C++ Executable Project" (RX231 custom target). Added "-mint-register=2 -msmall-data-limit=512" at Properties/C/C++ Build/Settings/Compiler/Command (rx-elf-gcc -mint-register=2 -msmall-data-limit=512) Added _gp to the linker script in .data section: .data : AT(_mdata) { __gp = .; _data = .; *(.data) *(.data.*) *(D) *(D_1) *(D_2) _edata = .; } > RAM Wrote a simple main and fast interrupt: // start code unsigned char Buffer[32]; unsigned char* pHead; unsigned char* pTail; volatile unsigned char Data; void ServiceFastRXI1(void) __attribute__ ((fast_interrupt,optimize("-O2"))); void ServiceFastRXI1(void) { *pHead++ = SCI1.RDR; *pTail++ = Data++; if(&Buffer[32] == pHead) { pTail = pHead = &Buffer[0]; } ICU.IER[15].BIT.IEN6 = 1; return; } void main(void) { int i; pTail = pHead = &Buffer[0]; i = (int)&ServiceFastRXI1; return; } // end code The compiled interrupt becomes: 19:../src/MTX.c **** void ServiceFastRXI1(void) __attribute__ ((fast_interrupt,optimize("-O2"))); 20:../src/MTX.c **** void ServiceFastRXI1(void) 21:../src/MTX.c **** { 9 .loc 1 21 1 view -0 10 ; Note: Fast Interrupt Handler 11 0000 6E 15 pushm r1-r5 12 .LCFI0: 22:../src/MTX.c **** *pHead++ = SCI1.RDR; 13 .loc 1 22 2 view .LVU1 14 .loc 1 22 8 is_stmt 0 view .LVU2 15 0002 FB 52 00 00 00 00 mov.L #_pHead, r5 16 0008 EC 53 mov.L [r5], r3 23:../src/MTX.c **** *pTail++ = Data++; 17 .loc 1 23 17 view .LVU3 18 000a FB 12 00 00 00 00 mov.L #_Data, r1 19 .loc 1 23 8 view .LVU4 20 0010 FB 42 00 00 00 00 mov.L #_pTail, r4 22:../src/MTX.c **** *pHead++ = SCI1.RDR; 21 .loc 1 22 8 view .LVU5 22 0016 71 32 01 add #1, r3, r2 23 0019 E3 52 mov.L r2, [r5] 22:../src/MTX.c **** *pHead++ = SCI1.RDR; 24 .loc 1 22 17 view .LVU6 25 001b FB 2E 20 A0 08 mov.L #0x8a020, r2 26 0020 89 2A mov.B 5[r2], r2 22:../src/MTX.c **** *pHead++ = SCI1.RDR; 27 .loc 1 22 11 view .LVU7 28 0022 C3 32 mov.B r2, [r3] 29 .loc 1 23 2 is_stmt 1 view .LVU8 30 .loc 1 23 17 is_stmt 0 view .LVU9 31 0024 CC 12 mov.B [r1], r2 32 .loc 1 23 8 view .LVU10 33 0026 EC 43 mov.L [r4], r3 34 .loc 1 23 17 view .LVU11 35 0028 71 2C 01 add #1, r2, r12 36 .loc 1 23 8 view .LVU12 37 002b 71 3B 01 add #1, r3, r11 38 .loc 1 23 17 view .LVU13 39 002e C3 1C mov.B r12, [r1] 40 .loc 1 23 8 view .LVU14 41 0030 E3 4B mov.L r11, [r4] 42 .loc 1 23 11 view .LVU15 43 0032 C3 32 mov.B r2, [r3] 24:../src/MTX.c **** if(&Buffer[32] == pHead) 44 .loc 1 24 2 is_stmt 1 view .LVU16 45 .loc 1 24 4 is_stmt 0 view .LVU17 46 0034 EC 53 mov.L [r5], r3 47 0036 74 03 00 00 00 00 cmp #_Buffer+32, r3 48 003c 20 15 beq .L5 25:../src/MTX.c **** { 26:../src/MTX.c **** pTail = pHead = &Buffer[0]; 27:../src/MTX.c **** } 28:../src/MTX.c **** ICU.IER[15].BIT.IEN6 = 1; 49 .loc 1 28 2 is_stmt 1 view .LVU18 50 .loc 1 28 23 is_stmt 0 view .LVU19 51 003e FB 5E 00 70 08 mov.L #0x87000, r5 52 0043 CE 54 0F 02 mov.B 527[r5], r4 53 0047 78 64 bset #6, r4 54 0049 CB 54 0F 02 mov.B r4, 527[r5] 29:../src/MTX.c **** return; 55 .loc 1 29 2 is_stmt 1 view .LVU20 30:../src/MTX.c **** } 56 .loc 1 30 1 is_stmt 0 view .LVU21 57 004d 6F 15 popm r1-r5 58 004f 7F 94 rtfi Note that this trashes both r11 and r12... /Henrik
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Interrupt routine trashes registers (GCC for Renesas RX)
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